A data processing apparatus may have a data array for storing data, such as a cache or buffer. It is common for data to be divided logically into “ways” and for data to be allocated to entries of the data array using an allocation scheme in which a data value with a particular address can only be allocated to a limited set of entries selected based on the address of the data value, the set comprising one entry from each way. For example, a set-associative cache allocates data to the cache in this way. Typically a tag value associated with each entry identifies which data value has been stored in the corresponding entry. When a data value needs to be updated in the data array, then the tag values of the corresponding set of entries are read to determine which entry stores the data value to be updated, and then a write request is issued to write the updated value to the appropriate entry of the data array.
In some applications, the data array may need to be accessed reasonably frequently and so providing sufficient access bandwidth can be a challenge. One way to provide more bandwidth is to divide up the entries of the data array into banks which may be accessed independently and simultaneously. This allows accesses to entries in different banks to be made in parallel, increasing the number of accesses that can be performed in a given time. However, banking comes at a cost of requiring more physical memories and associated wiring. More physical memories are undesirable because they increase circuit area and consume more power, due to the additional sense amplifiers and wiring required for the additional memories. Also the physical layout of a greater number of memories is more difficult to implement, and wiring congestion at the interfaces for each memory becomes a challenge.
Therefore, the present technique seeks to provide a more area and energy efficient technique for increasing access bandwidth for a data array.